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FPGA-Accelerated HFT Gateway

Verilog / Rust / C++ / Artix-7 / RP2040

A proof-of-concept trading pipeline built on hobbyist hardware. An RP2040 microcontroller plays the exchange, streaming orders over SPI to an Artix-7 FPGA that plays the bank's gateway, holding the order book and enforcing risk checks entirely in logic, while a terminal dashboard shows the state live. The point is to measure how deterministic tick-to-trade latency gets when the hot path is hardware instead of software.

System Architecture

Responsibilities split across three hardware tiers to optimize for latency and determinism: a Rust dashboard on the host PC for visualization, the RP2040 as a binary feed handler and traffic generator, and the FPGA holding the matching engine and pre-trade risk checks. The RP2040 communicates with the FPGA via a 4MHz SPI link, transmitting 64-bit packets: a 16-bit sequence number, an 8-bit command (PLACE / RESET / SET_MAX / SET_MIN), a 32-bit price, and an 8-bit additive checksum. The FPGA acts as an SPI slave, bringing the asynchronous SPI signals into the 100MHz system clock domain through triple-flop synchronizers with edge detection before deserializing the stream and processing orders in hardware. The bitstream is built with the open-source F4PGA (Yosys/VPR) flow targeting a Basys3 board, and the RTL (sortedness and risk checks) is verified via SymbiYosys formal verification and directed testbenching.

System Architecture Diagram
Fig 1. High-level topology. The RP2040 generates pseudo-random market data ("Tick") and measures the hardware round-trip time ("Trade") to the microsecond level. The FPGA maintains the order book state in registers. The PC displays results in real-time.

Hardware Matching Engine (Verilog)

The core logic is a Systolic Array Order Book implemented in Verilog. Unlike software implementations that require pointer chasing (Linked Lists) or rebalancing (RB-Trees), this design utilizes a parallel register array. On every clock cycle, each cell in the array compares the incoming price against its current stored value and its neighbor's value.

This allows for O(1) insertion time from the perspective of the control logic. The sorting invariant \(B_0 \ge B_1 \ge \dots \ge B_N\) is maintained automatically by the hardware structure. The state machine also enforces pre-trade risk limits (Max/Min Price) and verifies checksums before allowing an order to mutate the book state. 

always @(posedge clk) begin
    if (rst) begin
        for (i=0; i<DEPTH; i=i+1) bins[i] <= 0;
    end else if (insert_en) begin
        // Parallel Compare-and-Shift Logic
        if (new_price > bins[0]) bins[0] <= new_price;
        for (i = 1; i < DEPTH; i = i + 1) begin
            if (new_price <= bins[i-1] && new_price > bins[i]) 
                bins[i] <= new_price; // Insert Here
            else if (new_price > bins[i-1]) 
                bins[i] <= bins[i-1]; // Shift Down
        end
    end
end
Fig 2. The Systolic Array update logic in Behavioral Verilog. All bins update simultaneously. If a new high bid arrives, it overwrites the current slot and pushes existing bids down the array in a single clock transition.

Control Logic & RTL

The control path is governed by a finite state machine keyed off the rising edge of chip select. It transitions from Idle to Validation upon packet reception, verifying the 8-bit checksum against the payload; valid packets trigger the Execute state, which either drives the write-enable for the systolic array (subject to the min/max risk registers) or updates those risk parameters. Every outcome is encoded in a status register (OK, Bad Checksum, Risk Reject). Because SPI is full-duplex, the FPGA preloads its TX shift register while chip select is idle with a magic word, the last accepted sequence number, the status code, and the current top-of-book bid. Each transaction therefore reads back the result of the previous one without any extra round trip.

RTL Schematic
Fig 3. Logic representation of the FSM and top-level module. The schematic highlights the data path from the SPI deserializer shift registers into the checksum validator and finally the matching engine. Image generated with TerosHDL.
RTL Schematic
Fig 4. Gate representation of the top-level module. This highlights the relatively narrow width of the module, demonstrating parallelism and low-cycle processing. The grey rectangle highlights the systolic array. More importantly, it is a fantastic reminder of how incredible it is that a simple bitstream can encode all of this custom decision logic to be run on premade silicon in deterministic time. Image generated with TerosHDL.

Feed Handler & Telemetry (C++ / Rust)

The RP2040 firmware is C++ and uses both cores: Core 1 is a dedicated SPI driver fed through an inter-core queue, while Core 0 runs a "Random Walk" market simulation. To test the FPGA's rejection paths, the simulator regularly injects faults: corrupted checksums and out-of-band prices at roughly 1% rates, plus periodic engine resets and risk-limit reconfiguration. It also measures Tick-to-Trade latency by capturing the microsecond timestamp t0 before assertion of Chip Select and t1 after the SPI transaction completes.

Telemetry is emitted as magic-prefixed binary structs over USB-UART and consumed by a Rust application using the Ratatui library. This TUI logs per-packet command, status (Checksum OK/Fail, Risk Reject), and hardware-measured latency, tallies the rejection counters so their proportions are visible at a glance, and plots the FPGA's internal "Top of Book" against the generated market price in real-time, visualizing inefficiency.